Computer processors are continuously evolving, and several processor architectures like x86 and ARM64 created a name for themselves. There are three primary processor architectures used in today’s environments: 32-bit (x86) and 64-bit (x86-64, IA64, ARM, and AMD64). These architectures differ in the data-path width, integer length, and memory address width that the processor is capable to work with.
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We will check out the best options among the different architectures and focus on understanding the differences between the three architectures viz RISC-V vs. ARM vs. x86.
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The differences between the three architectures, viz RISC-V vs. ARM vs. x86, are quite subtle in nature. The actual differences lie in different factors, including how the architectures address the memory, how exceptions are taken care of, and a host of other parameters.
In this post, we will focus on understanding the factors such as reduced instruction set computing (RISC) and complex instruction set computing (CISC). We will also consider these factors’ impact on performance and power consumption.
the cost of hardware and software engineering, additional mask sets, or lost margin can easily offset the value of a lower license fee and/or royalty fees.
The X86 is a platform offered by Intel and is also (licensed) implemented on AMD processors. The ARM processors and IP are ideally offered by ARM limited. The RISC-V International organization developed the RISC-V architecture.
The major difference is that X86 and ARM are based on proprietary IP and sold and licensed by Intel, AMD, and ARM. The RISC-V is an open-source specification platform.
(Image: RISC-V International)
ARM is less “sterile” RISC than SPARC and MIPS and contains some practical “CISC-like” features that allow writing the same code with fewer instructions. The 32-bit ARM also had “thumb” mode, which has half-length(16-bit) encoding for the most common instructions.
Denser code means less instruction memory, less energy wasted for fetching instructions, and better cache hit ratios %.
Because ARM allowed writing the same code in a much smaller space, it was suitable for small devices with tight memory space and bandwidth constraints, such as the early mobile phones (Palm / Windows Mobile).
For example, in the original 32-bit ARM, there were instructions to store or load multiple registers at once, making the register saving and restoring code much shorter. In ARMv8, this has been limited to two registers per instruction.
Manufacturing any new processor design has risks. However, with a licensable core, most of the risk is with the first few designs.
And in the original 32-bit ARM, almost all instructions could be predicated, clearing the need for many branches. On the other hand, MIPS and SPARC branches even had a delay slot, often leading to extra instruction being wasted after a branch.
PPC & Power is also not as “refined” RISC as MIPS and SPARC; it lacks the most absurd features of “pure RISCs” like delay slots – and it has also survived much better, Power is well alive in IBMs servers while SPARC and MIPS are virtually dead.
RISC has simple instructions that can be executed in a single instruction length. That would mean you will need multiple instructions for completing a task. Using a CISC processor, you will find that a similar job can be completed within a few instructions.
RISC-V is an open standard instruction set architecture based on designated RISC principles. Unlike most different ISA designs, RISC-V is delivered under open source licenses that do not need fees to use.
CISC computing can handle the task in just a few instructions, while RISC computing can take many instructions to complete.
A good example can be the multiplication of two numbers. Let us compare how the two processors can handle the task.
A CISC processor can handle the task with the following command line –
MUL XXX1, XXX2
In the case of a RISC processor, the instruction cannot be completed in one single line or command. It will need you to have multiple instructions –
Load A, XXX1
Load B, XXX2
MUL A, B
Store XXX1, A
In a CISC processor, the instructions are performed on memory directly. However, in the case of a RISC processor, operatives such as MUL are performed on registers and not on memory directly.
The RISC computations are simple; thus, they would need less Power to execute. The CISC processors would reduce the number of instructions per program, but this is done at the cost of several computer clock cycles per instruction.
You would find an exactly opposite scenario in the case of the RISC processors. It makes use of simple instructions per clock cycle, and thus the number of instructions will be higher. It can be made clear with the following image.
You can improve the performance by minimizing the number of instructions per program or reducing the number of cycles per instruction. As you would see, the RISC approach would reduce the overall power consumption but can lower the performance level.
The security of a processor is defined by the privilege rings or the protection rings. These are the hierarchical domains used to protect the data and keep the processor secure.
The rings are responsible for faults, improving fault tolerance, and improving security. The rings are arranged in a differential status and involve several options that would include several options from faults, improve fault tolerance, and improve security.
The X86 architecture comes with four levels of privilege rings. The ARM V7 architecture makes use of three privilege rings.
This would include applications, operating systems, and hypervisor. You would also find an isolation mechanism used in both ARM and RISC-V. ARM makes use of hardware-based security, while RISC V processors make use of software-defined isolation domains.
In the case of the ARM devices and platforms, you would see OP-TEE technology. The OP-TEE is an open-source trusted execution environment that implements the ARM TrustZone technology.
RISC makes use of the RISC-V MultiZone security software. This is a smaller model and therefore is quite faster in terms of performance. You would find that RISC V has several security mechanisms implemented in the platform.
This will include our levels of privilege rings, secure interrupt processing, and physical memory protection (PMP) mechanism.
You would also find the options such as cryptographic libraries, roots of trust, and multi-domain TEEs. The RISC V platform has a more extensive and diverse community.
They keep studying the security environment and identify the security loopholes. Once a risk is identified, it is shared with the community so that experts can develop fixes.
The Predicated Execution is what would provide you access to the execution of service only if a specific condition is true. You will find that the ARM and x86 processors use several formats of predicated execution.
Yet another option that you would find much impressive on the processors is the Macro Operation Fusion. This one is a hardware execution optimization technique and uses several macro instructions amalgamated into one.
If you are using an ARM processor, you will find it supporting a good number of micro-op fusion operations. This can be useful and practical in letting you use predicated execution set with the perfect instructions.
The RISC V instruction does not support predicated execution. Experimental BOOMv3 out-of-order speculative RISC-V processor uses several options such as reduced instruction set with micro-operation fusing to implement predicated execution.
All three processor architectures, such as ARM, x86, and RISC-V, support the virtualization of CPUs and memory. The RISC V does not, however, support the virtualization of I/Os.
In the case of Intel, you will find it offering you support for Virtualization Technologies or VT. On the other hand, AMD comes with the support for core side virtualization for the label AMD-V. Intel and AMD come with different approaches of their own.
The ARM virtualization extensions used in the case of the X86 processors are also used on the ARM processors. ARM virtualization extensions enable the hardware to virtualize a CPU using a hypervisor. You can make use of the virtual CPUs for running multiple operating systems.
In the case of RISC V, you would find virtualization of CPUs handled with the sensitive registers and instructions used in a host mode. However, the RISC V virtualization is still an ongoing process and will be developed better.
You will also find the RISC V providing support for memory virtualization using multi-stage page tables. This is quite an equivalent option compared to the ones available on X86 and ARM.
You would also find RISC V offering support for identical page table entry formats for both guest and host tables. The I/O virtualization may not be specified as of now on RISC V.
Let us now check out the options for RISC V and ISA customization. In addition to the base ISA and standard customizations, you would find the platform supporting custom ISA customizations.
ARM is not designed for using the custom ISA execution. However, things are changing today, and ARM is implementing the Custom ISA executions of late. The X86 architecture does not support custom ISA executions and is primarily a closed system.
The use of custom ISA implementation can be pretty exciting for a few specific use cases. You can even use the processors for custom extensions for running generic RISC-V software.
The significant differences between X86, ARM, and RISC V microprocessors can be pretty handy in understanding the concept better. The x86 processors from AMD and Intel dominate the realm of computers and servers.
If you are looking forward to the best experience in smartphones and tablets, the ARM processors from Apple and Qualcomm should be quite an excellent option.
The Linux operating system already supports RISC-V architecture
You would also find the ARM processors an excellent option for embedded applications. However, of late, the embedded systems are increasingly opting for the RISC V systems.
You would also find it quite impressive in several application areas, including automotive systems, disk drives, artificial intelligence, and machine learning applications.
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